Semiconductor Supply Chain Bottlenecks

Definition

The cascading physical constraints — from EUV lithography tools to memory fabs to advanced packaging — that limit how fast AI compute capacity can scale, regardless of demand or capital availability.

Key Points

• The bottleneck shifts over time: CoWoS (2023) → power/data centers (2024-25) → logic wafers and memory (2026+) → EUV tools (2028-30) (dwarkesh dylan patel interview)
• ASML produces ~70 EUV tools/year, growing to ~100 by 2030; 3.5 tools = 1 GW of AI chips; ~700 cumulative by 2030 = 200 GW theoretical max (dwarkesh dylan patel interview)
• Nvidia has secured 70%+ of TSMC N3 capacity by 2027 by committing earlier than Google/Amazon (dwarkesh dylan patel interview)
• 30% of Big Tech CapEx now goes to memory; DRAM prices tracking 4-5x YoY increases (dwarkesh dylan patel interview, great gpu shortage rental capacity)
• Memory crunch is destroying consumer demand: smartphone volumes may drop from 1.1B to 500-600M/year (dwarkesh dylan patel interview)
• Memory fabs take 2 years to build; no quick fix (dwarkesh dylan patel interview)
• OEMs repricing AI servers above underlying component cost increases, further tightening rental market (great gpu shortage rental capacity)
• LP30 chip (Groq) fabricated on Samsung SF4 — not constrained like TSMC N3, representing incremental capacity (nvidia inference kingdom expands)

Open Questions

• Will ASML scale beyond 100 EUV tools/year? They've historically been conservative.
• Can 3D DRAM fundamentally change the memory bottleneck by end of decade?
• Will Elon's TeraFab / Samsung partnership meaningfully diversify the supply chain?
• At what point does the semiconductor supply chain become a national security chokepoint?

Related Concepts

• gpu and compute economics
• inference architecture and scaling
• data center infrastructure